This invention relates to integrated circuit packages; and more particularly, it relates to high density integrated circuit modules in which a plurality of integrated circuit chips are stacked on top of one another.
In the prior art, a wide variety of integrated circuit packages have been described. See, for example, U.S Pat. Nos. 4,643,935 and 4,807,019. In the former, only a single integrated circuit chip is contained in the package; while in the latter, multiple integrated circuit chips are contained in the package. However, in the '019 multichip package, the chips are not stacked on top of one another; instead they lie side by side in a plane. Thus, the chip packaging density of the package is substantially lower than that of a chip stack.
In the prior art, a chip stack is described in U.S. Pat. No. 4,525,921. There, the stacked chips are indicated by reference numeral 14 in FIG. 2. Each of the chips contains integrated circuits, and input/output signals to/from those circuits are carried by microscopic conductors 68 to one face of the stack.
All of the microscopic conductors 68 are inherently thin and fragile since they are formed as part of the integrated circuitry that is on the chips. Typically, conductors that are formed within an integrated circuit are only about 1 um to 4 um wide and 0.1 um to 0.2 um thick. This then presents the problem of how to interconnect the ends of the conductors 68 from all of the chips along the face of the stack.
In particular, it is not possible to interconnect the ends of the conductors 68 by simply: (a) depositing an insulating layer over the face of the stack to which they run, (b) opening via holes in that insulating layer which exposes just the ends of the conductors, and (c) patterning interconnecting conductors on the insulating layer and in the via holes. Such via holes would expose both the ends of the conductors 68 and a portion of the sides of the chips. Thus, the interconnecting conductors which are formed in the via holes will also be shorted to the sides of the chips.
To overcome the above problem, patent '921 discloses a four-step process by which the conductors 68 can be interconnected without producing shorts to the sides of the chips. These steps are illustrated in FIGS. 5A-5D; and they consist of lapping, etching, passivating, and re-lapping the face of the chip stack to which the conductors 68 extend.
However, those four steps add to the overall complexity and cost of the manufacturing the stack. Also, after the etching step, the thin, fragile conductors 68 protrude from the face of the stack; so they can easily be bent or broken. If any of the protruding conductors 68 are bent, they will "shadow" the adjoining silicon chip during the passivation step and thereby cause a void in the passivation layer. Such a void will cause a short circuit to the side of the chip when metallization for interconnecting the I/O conductors 68 is subsequently applied.
Accordingly, a primary object of the invention is to provide an improved architecture for a stack of integrated circuit chips in which all of the above problems are avoided.